VHDL code for D Flip flop to use as counter

[kumarji]

I am working on VHDL Libero software. I need to design a counter using D Flip Flop. Can anyone provide the code for that?

 

[mjuneja]

process(rst,clk,cntr)
begin
  if(rst = '0') then
    cntr <= (others => '0');
  elsif(rising_egde(clk)) then
    cntr <= cntr + 1;
  end if;
end process;

This code is an example of synchronous MOD 2^n counter with clk as clock, rst as asynchronous reset and cntr can be defined as unsigned(n-1 downto 0) in your code declaration.