vhdl code for copying an array of elements

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jincyjohnson

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I have an array variable 'choice'. It stores an array of 8 bit elements. I want to transfer each 8 bit element to another variable 'vector' in each clock transfer. This is repeated until the count 'ctt1' becomes 17. But in each transfer only first 4 bits are transferred and remaining 4 are uuuu.

eg: choice=[00000001, 01010101, 11110000, 10001111]

here i get the output as

1st clk; vector<=0000uuuu
2nd clk; vector<=0101uuuu
3rd clk; vector<=1111uuuu
4th clk; vector<=1000uuuu

the coding is written as

process(ready,chain)
variable ctt1:integer:=0;
begin
if ready='1' then
ctt1:=ctt1+1;
if ctt1<17 then
vector(0 to 7)<=chain(ctt1-1);
end if;
end if;
end process;

plz reply
 


why are you using vector(0 to 7)<=chain(ctt1-1).Use a case statement which has four states corresponding to above choices.Take one more 2 bit counter which is incremented based on ctt1<17 condition.Then vector will be repeatedly assigned to choices for every clock until ctt1 becomes 17.
 

The above given patterns are shown as an example. Actually this is a pseudorandom pattern generator. There are 4 chains.chain1,---chain4. The output depends on a given seed vector. Each pattern of a hain are of 8 bits. Also each chain produces 16 patterns.
eg:chain1=[10101010,11111111,-----0010000]
chain2=[00001010,01010010.------11100010]
chain3=[01000000,11100110,-----00011000]
chain4=[11111100,11111110,------01011111]

At each clock cycle a pattern (of 8 bits) is generated in each chain.Any one of the chain output is given to the variable vector. If we take chain2 output, then the vector becomes

vector=0000uuuu (1st clk)
vector= 0101uuuu(2nd clk)
vector=1110uuuu(16th clk)
plz reply
 

jincyjohnson said:
The above given patterns are shown as an example. Actually this is a pseudorandom pattern generator.
vector=0000uuuu (1st clk)
vector= 0101uuuu(2nd clk)
vector=1110uuuu(16th clk)
plz reply
Click to expand...

upload the code you have written and on what basis you are selecting chains..
 

Are you writing VHDL for simulation? Counting in a combinational process isn't synthesizable.
 

yes, first i have to simulate it. But i didn't get the correct output.How can we synthesize it.plz reply.
 

We are still waiting for meaningful (complete) code.

For a synthesizable design, you'll need to perform the counting in a clock synchronous process.
 

Code VHDL - [expand]
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Package my_pack is         
        type arr1 is array(0 to 15) of std_logic_vector(0 to 7);       
        type arr2 is array(0 to 31) of std_logic_vector(0 to 7);    
    end package;
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;  
use ieee.math_real.all;
use work.my_pack.all;
 
entity fcsty is
port( clk1     : in std_logic;
        clk2     :in std_logic;
        seed      :in std_logic_vector(0 to 4);
       fault     : inout std_logic;     
        fcoverage:out real;
          choice:in std_logic_vector(3 downto 0));        
end fcsty;
 
architecture behavioral of fcsty is
component pattern is
           port(clk1:in std_logic;
                clk2:in std_logic;        
                seed:in std_logic_vector(0 to 4);
               ready:out std_logic:='0';
               chain1,chain2,chain3,chain4:inout arr1
                    );             
end component;    
 
component fcs is
port(  clk2:in std_logic;
    A  : in std_logic_vector(3 downto 0);  
    B: inout std_logic_vector(3 downto 0);
    enable:in std_logic:='0';    
      M_Out  : inout std_logic_vector(7 downto 0):="00000000" );     
end component;
 
component fcst is
port( clk2:in std_logic;
    choice   : in std_logic_vector(3 downto 0); 
     A:in std_logic_vector(3 downto 0);
    B : inout std_logic_vector(3 downto 0);  
    fout:inout std_logic_vector(7 downto 0):="00000000";
    fault:inout std_logic;  
     cs,nss:inout integer;
     enable:in std_logic:='0';
     fcoverage:out real);
end component;
 
   signal ref_out,test_out:std_logic_vector(7 downto 0):="00000000";
   signal ready:std_logic:='0';
   signal chain1,chain2,chain3,chain4:arr1;    
   signal vector:std_logic_vector(0 to 7):="00000000";
   signal ct:integer:=0;         
     signal cs,nss:integer:=0;      
    begin
               x1:pattern port map(clk1,clk2,seed,ready,chain1,chain2,chain3,chain4);
        x2:fcs port map(clk2,vector(0 to 3),vector(4 to 7),ready,ref_out);
        x3:fcst port map(clk2,choice,vector(0 to 3),vector(4 to 7),test_out,fault,cs,nss,ready,fcoverage); 
 
process(ref_out,test_out,clk2,vector,choice,ready,fault,cs,nss)          
         
          begin          
              if ref_out=test_out then
                  fault<='0';
              else
                  fault<='1';
              end if;                 
          end process;
                  process(ready,chain2)
           variable ctt1:integer:=0;              
          begin                                              
         if ready='1' then              
                  ctt1:=ctt1+1;
                  if ctt1<17 then
                  vector<=chain2(ctt1-1);             
               end if;                               
             end if;        
            end process;
          end behavioral;
 
Last edited by a moderator:

jincyjohnson,

You need to use the clock clk2 as the process sensitivity list. As FvM stated you can't synthesize the counter in the combinational process.

jincyjohnson said:
yes, first i have to simulate it. But i didn't get the correct output.How can we synthesize it.plz reply.
Click to expand...
I wouldn't try to fix the combinational process as you will eventually have to rewrite it completely to make it synthesizable.

Regards
 

Code: 
library ieee;
    use ieee.std_logic_1164.all;   
	 
    Package my_pack is         
        type arr1 is array(0 to 15) of std_logic_vector(0 to 7);       
        type arr2 is array(0 to 31) of std_logic_vector(0 to 7);    
    end package;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;  
use ieee.math_real.all;
use work.my_pack.all;

entity fcsty is
port( clk1     : in std_logic;
        clk2     :in std_logic;
        seed      :in std_logic_vector(0 to 4);
       fault     : inout std_logic;		
        fcoverage:out real;
		  choice:in std_logic_vector(3 downto 0));		  
end fcsty;

architecture behavioral of fcsty is
component patternn is
           port(clk1:in std_logic;
                clk2:in std_logic;        
                seed:in std_logic_vector(0 to 4);
               ready:out std_logic:='0';
               chain1,chain2,chain3,chain4:inout arr1
					);             
end component;    

component fcs is
port(  clk2:in std_logic;
    A  : in std_logic_vector(3 downto 0);  
    B: inout std_logic_vector(3 downto 0);
    enable:in std_logic:='0';	 
      M_Out  : inout std_logic_vector(7 downto 0):="00000000" );	 
end component;

component fcst is
port( clk2:in std_logic;
    choice   : in std_logic_vector(3 downto 0); 
	 A:in std_logic_vector(3 downto 0);
    B : inout std_logic_vector(3 downto 0);	 
    fout:inout std_logic_vector(7 downto 0):="00000000";
	fault:inout std_logic;	
	 cs,nss:inout integer;
	 enable:in std_logic:='0';
 fcoverage:out real);
end component;

   signal ref_out,test_out:std_logic_vector(7 downto 0):="00000000";
   signal ready:std_logic:='0';
   signal chain1,chain2,chain3,chain4:arr1;    
   signal vector:std_logic_vector(0 to 7):="00000000";
   signal ct:integer:=0;		 
	 signal cs,nss:integer:=0;		
    begin
              
-- ------------------------------------------------------------------------------------  
 
				
		  x1:patternn port map(clk1,clk2,seed,ready,chain1,chain2,chain3,chain4);
        x2:fcs port map(clk2,vector(0 to 3),vector(4 to 7),ready,ref_out);
        x3:fcst port map(clk2,choice,vector(0 to 3),vector(4 to 7),test_out,fault,cs,nss,ready,fcoverage); 

process(ref_out,test_out,clk2,vector,choice,ready,fault,cs,nss)          
         
          begin
if rising_edge(clk2)then             
                              			 
              if ref_out=test_out then
                  fault<='0';
              else
                  fault<='1';
              end if; 
end if;				  
          end process;
         		  process(ready,chain2,clk2)
           variable ctt1:integer:=0;			  
          begin
if rising_edge(clk2)then                    
        		 
         if ready='1' then              
                  ctt1:=ctt1+1;
                  if ctt1<17 then
                  vector<=chain2(ctt1-1);             
               end if;                               
             end if;		
end if;
            end process;
          end behavioral;

i insert the clk inside process. But i didn't get the output. only the first 4 bits of the total 8 bit is transferred. The remaining bits are 'uuuu'. plz reply

- - - Updated - - -


the output is like this
 
Last edited:

i insert the clk inside process. But i didn't get the output. only the first 4 bits of the total 8 bit is transferred. The remaining bits are 'uuuu'. plz reply
Click to expand...

Signal vector(4 to 7) is connected to inout ports of components fcs and fcst. The most likely explanation is that the "UUUU" bits are driven by one or both component(s).

Enough guessing about incomplete documented designs for the time being.
 

    V

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