Oct 17, 2014 #1 K krisdan Banned Joined Oct 17, 2014 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Visit site Activity points 0 Please gurus in the house can anyone help me with the code for vhdl code for 4-bit parallel access shift registers and its test bench... Am very new to vhdl and i really need the stuff..waiting for your urgent replies Attachments 4 BIT.PNG 55.6 KB · Views: 229
Please gurus in the house can anyone help me with the code for vhdl code for 4-bit parallel access shift registers and its test bench... Am very new to vhdl and i really need the stuff..waiting for your urgent replies
Oct 17, 2014 #2 andre_luis Super Moderator Staff member Joined Nov 7, 2006 Messages 9,654 Helped 1,191 Reputation 2,401 Reaction score 1,219 Trophy points 1,403 Location Brazil www.linkedin.com Activity points 55,989 Had you took a look on forum history ? There are some threads which can help you to start a design, like that : Re: vhdl code help shift registers
Had you took a look on forum history ? There are some threads which can help you to start a design, like that : Re: vhdl code help shift registers
Oct 17, 2014 #3 nick123 Member level 2 Joined Aug 16, 2014 Messages 53 Helped 3 Reputation 8 Reaction score 3 Trophy points 8 Visit site Activity points 334 Code VHDL - [expand]1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 LIBRARY ieee; USE ieee.std_logic_1164.all; ------------------------------------------------ ENTITY shiftreg4 IS PORT ( P: IN STD_LOGIC_VECTOR (3 DOWNTO 0); Clock:IN STD_LOGIC; LOAD,I:IN STD_LOGIC; Q:BUFFER IN STD_LOGIC _VECTOR (3 DOWNTO 0) ); END shiftreg4; ------------------------------------------------ ARCHITECTURE arch OF shiftreg4 IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'event AND Clock='1'; IF LOAD='1' THEN Q<=P; ELSE Q(0)<=Q(1); Q(1)<=Q(2); Q(2)<=Q(3); Q(3)<=I; END IF END PROCESS; END arch; ------------------------------------------------ Last edited by a moderator: Oct 17, 2014
Code VHDL - [expand]1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 LIBRARY ieee; USE ieee.std_logic_1164.all; ------------------------------------------------ ENTITY shiftreg4 IS PORT ( P: IN STD_LOGIC_VECTOR (3 DOWNTO 0); Clock:IN STD_LOGIC; LOAD,I:IN STD_LOGIC; Q:BUFFER IN STD_LOGIC _VECTOR (3 DOWNTO 0) ); END shiftreg4; ------------------------------------------------ ARCHITECTURE arch OF shiftreg4 IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'event AND Clock='1'; IF LOAD='1' THEN Q<=P; ELSE Q(0)<=Q(1); Q(1)<=Q(2); Q(2)<=Q(3); Q(3)<=I; END IF END PROCESS; END arch; ------------------------------------------------