vhdl code for 2d 8x8 dct using distributed arithmetic

respected sir/madam,
i am doing my mtech project in dct watermarking.
but i am unable to write the code of da based dct in vhdl.
i hope a favorable support from anyone in this forum..

What have you done so far and whats the problem?

thanks for ur concern trickydicky.
the main problem i faced was
1.handling signed and unsigned number in vhdl
2. real number mutiplication (signed output needed).

post the code with the problems.

library IEEE;
library work;
use work.div.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.ALL;
use IEEE.std_logic_signed.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dct1 is
Port ( x0 : in STD_LOGIC_VECTOR (7 downto 0);
x1 : in STD_LOGIC_VECTOR (7 downto 0);
x2 : in STD_LOGIC_VECTOR (7 downto 0);
x3 : in STD_LOGIC_VECTOR (7 downto 0);
x4 : in STD_LOGIC_VECTOR (7 downto 0);
x5 : in STD_LOGIC_VECTOR (7 downto 0);
x6 : in STD_LOGIC_VECTOR (7 downto 0);
x7 : in STD_LOGIC_VECTOR (7 downto 0);
y0 : out STD_LOGIC_VECTOR ( 19 downto 0);
y1 : out STD_LOGIC_VECTOR ( 19 downto 0);
y2 : out STD_LOGIC_VECTOR ( 19 downto 0);
y3 : out STD_LOGIC_VECTOR ( 19 downto 0);
y4 : out STD_LOGIC_VECTOR ( 19 downto 0);
y5 : out STD_LOGIC_VECTOR (19 downto 0);
y6 : out STD_LOGIC_VECTOR ( 19 downto 0);
y7 : out STD_LOGIC_VECTOR (19 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end dct1;

architecture Behavioral of dct1 is
constant p : STD_LOGIC_VECTOR (7 downto 0):="00100011";
constant m : STD_LOGIC_VECTOR (7 downto 0):="00101110";
constant n : STD_LOGIC_VECTOR (7 downto 0):="00010011";
constant a : STD_LOGIC_VECTOR (7 downto 0):="00110001";
constant b : STD_LOGIC_VECTOR (7 downto 0):="00101001";
constant c : STD_LOGIC_VECTOR (7 downto 0):="00011011";
constant d : STD_LOGIC_VECTOR (7 downto 0):="00001001";

constant a1_2 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";


signal s1,s2,s3,s4,s21,s23,s31:STD_LOGIC_VECTOR (19 downto 0);
signal d22,d24,d31,d11,d12,d13,d14 :STD_LOGIC_VECTOR (19 downto 0);
signal y00,y01,y02,y03,y04,y05,y06,y07:STD_LOGIC_VECTOR(19 downto 0);
signal d0,d1,d2,d3,d4,d5,d6,d7:STD_LOGIC_VECTOR(27 downto 0);
signal f0,f1,f2,f3,f4,f5,f6,f7:STD_LOGIC:='0';
---------------------------------------------------------------------------------------------------

begin

dct1rocess(clk)
begin
if (clk='1' and clk'event) then
if(rst='1') then
y0<="00000000000000000000";
y1<="00000000000000000000";
y2<="00000000000000000000";
y3<="00000000000000000000";
y4<="00000000000000000000";
y5<="00000000000000000000";
y6<="00000000000000000000";
y7<="00000000000000000000";
else

s1<=x0+x7;
s2<=x3+x4;
s3<=x2+x5;
s4<=x1+x6;

d11<=x0-x7;
d12<=x1-x6;
d13<=x2-x5;
d14<=x3-x4;

s21<=s1+s2;
d22<=s1-s2;
s23<=s3+s4;
d24<=s3-s4;
s31<=s21+s23;
d31<=s21-s23;


d0<= p*s31;
d4<= p*d31;
d2<=(d22*m)+(d24*n);
d6<= (d24*m)+(d22*n);
d1<=(d11*a)+(d12*b)+(d13*c)+(d14*d);
d3<=(d11*b)-(d12*d)-(d13*a)-(d14*c);
d5<=(d11*c)-(d12*a)+(d13*d)+(d14*b);
d7<=(d11*d)-(d12*c)+(d13*b)-(d14*a);

if(d0(27)='1') then
f0<='1';
d0<=not d0 +1;
end if;
if(d1(27)='1') then
f1<='1';
d1<=not d1+1;
end if;
if(d2(27)='1') then
f2<='1';
d2<=not d2+1;
end if;
if(d3(27)='1') then
f3<='1';
d3<=not d3+1;
end if;
if(d4(27)='1') then
f4<='1';
d4<=not d4+1;
end if;
if(d5(27)='1') then
f5<='1';
d5<=not d5+1;
end if;
if(d6(27)='1') then
f6<='1';
d6<=not d6+1;
end if;
if(d7(27)='1') then
f7<='1';
d7<=not d7+1;
end if;

--y0<=div_100(d0);
--y1<=div_100(d1);
--y2<=div_100(d2);
--y3<=div_100(d3);
--y4<=div_100(d4);
--y5<=div_100(d5);
--y6<=div_100(d6);
--y7<=div_100(d7);

--
--
--
--
y00<=restoring_divide(d0,"01100100");
y01<=restoring_divide(d1,"01100100");
y02<=restoring_divide(d2,"01100100");
y03<=restoring_divide(d3,"01100100");
y04<=restoring_divide(d4,"01100100");
y05<=restoring_divide(d5,"01100100");
y06<=restoring_divide(d6,"01100100");
y07<=restoring_divide(d7,"01100100");

if(f0='1') then
y0<=not y00 +1;
else
y0<=y00;
end if;

if(f1='1') then
y1<=not y01 +1;
else
y1<=y01;
end if;

if(f2='1') then
y2<=not y02 +1;
else
y2<=y02;
end if;

if(f3='1') then
y3<=not y03 +1;
else
y3<=y03;
end if;

if(f4='1') then
y4<=not y04 +1;
else
y4<=y04;
end if;

if(f5='1') then
y5<=not y05 +1;
else
y5<=y05;
end if;

if(f6='1') then
y6<=not y06 +1;
else
y6<=y06;
end if;

if(f7='1') then
y7<=not y07 +1;
else
y7<=y07;
end if;
end if;

end if;
end process;
end Behavioral;

- - - Updated - - -

actually in dct we have multiplication of real number with pixel values. but inorder to avoid the usage of real number, i have convert the real number to integer and finally divide the number with multiples of 10.
second problem faced was while we add s1<=x0+x7, the answer was wrong due to the problem of signed and unsigned....

So what is the problem? Can you post the testbench? why cant you just put a sign bit on the front of the unsigned number? the problem here is you're using the non-standard std_logic_signed library, so you cannot do signed and unsigned arithmatic in the same file. You need to use the signed/unsigned types from numeric_std, and then you have no problem (do not use std_logic_arith or std_logic_signed as they are not part of the VHDL standard)

You have also included math_real. Why? you cannot use it for synthesis.

hi, i think you'r thinking as software flow and write your code. you should turn your sight to the hardware flow. divide the dct algorithm to the smallest partition like "floating point add/sub" and "floating point mul" module and then build (not write) your primary dct block.