VHDL code error for assigning value to signal

kushal nandanwar · Sep 24, 2015

Code:

signal H0,H1,H2,H3 : std_logic_vector(7 downto 0) := (others => '0');


H0 <= 00000010;
H1 <= 00000001;
H2 <= 00000011;
H3 <= 00000100;

error

Entity <fir_4tap> compiled.
ERROR:HDLParsers:800 - "I:/Shivam/cla/cla/FIR/FIR.vhd" Line 109. Type of H0 is incompatible with type of 00000010.
ERROR:HDLParsers:800 - "I:/Shivam/cla/cla/FIR/FIR.vhd" Line 110. Type of H1 is incompatible with type of 00000001.
ERROR:HDLParsers:800 - "I:/Shivam/cla/cla/FIR/FIR.vhd" Line 111. Type of H2 is incompatible with type of 00000011.
ERROR:HDLParsers:800 - "I:/Shivam/cla/cla/FIR/FIR.vhd" Line 112. Type of H3 is incompatible with type of 00000100.

ads-ee · Sep 24, 2015

std_logic_vector needs double quotes:

Code:

H0 <= "00000010";
H1 <= "00000001";
H2 <= "00000011";
H3 <= "00000100";

Better invest in a VHDL book.

kushal nandanwar · Sep 25, 2015

ads-ee said:
std_logic_vector needs double quotes:

Code:

H0 <= "00000010"; H1 <= "00000001"; H2 <= "00000011"; H3 <= "00000100";

Better invest in a VHDL book.

Can I write like this, if I want to assign array

H0 <= "00000010","00000010";

ultimate_kc · Sep 25, 2015

You cannot assign array like that. it will show an syntax error

For declaring an array of 15rows and 15 coloumns :

Code:

type sample is array (15 downto 0) of std_logic_vector(15 downto 0);
signal sample_1 : sample;

if clk = '1' and clk'event then
   i <= i + 1;
   sample(i) <= data_in;
end if;

i think if you are using 'i' as std_logic_vector you need to convert 'i' into an integer as follows.

Code:

  sample(conv_integer(i)) <= data_in;

I hope this gives you an explanation.

TrickyDicky · Sep 25, 2015

kushal nandanwar said:
Can I write like this, if I want to assign array

H0 <= "00000010","00000010";

No you cannot, because H0 is a single 8 bit value, not an array.

- - - Updated - - -

ultimate_kc said:
You cannot assign array like that. it will show an syntax error

For declaring an array of 15rows and 15 coloumns :

type sample is array (15 downto 0) of std_logic_vector(15 downto 0);
signal sample_1 : sample;

if clk = '1' and clk'event then
i <= i + 1;
sample(i) <= data_in;
end if;

i think if you are using 'i' as std_logic_vector you need to convert 'i' into an integer as follows.
sample(conv_integer(i)) <= data_in;

I hope this gives you an explanation.

I dont quite know what you are trying to acheive? your code assigns a single value in the array on each clock cycle, is this what you intended? This example isnt very good as it doesnt make clear whether you're trying to create a ram or just and array. And I dont understand why you give an example using data_in to assign the i signal?

It also uses the non-standard conv_integer function.

dpaul · Sep 25, 2015

kushal nandanwar said:
Can I write like this, if I want to assign array
H0 <= "00000010","00000010";

You are seriously lacking even the basic VHDL knowledge, so please follow what 'ads-ee' has already said.

Better invest in a VHDL book.

VHDL code error for assigning value to signal

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VHDL code error for assigning value to signal

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