Mercury
Member level 3
Detecting 8 bit changes
Hello!
I would like to make a VHDL circuit ( xilinx 9500 cpld, webpack 5.2 ) that would set the IRQ output if any of the eight inputs ( Din: in std_logic_vector(7 downto 0); ) changes it state. The IRQ should be cleared at the rising edge of the STR input. The problem is that I cannot detech vector input changes and I cannot change states of one output from two processes.
George
Hello!
I would like to make a VHDL circuit ( xilinx 9500 cpld, webpack 5.2 ) that would set the IRQ output if any of the eight inputs ( Din: in std_logic_vector(7 downto 0); ) changes it state. The IRQ should be cleared at the rising edge of the STR input. The problem is that I cannot detech vector input changes and I cannot change states of one output from two processes.
George