VHDL circuit for detecting 8 bit inputs changes

[Mercury]

Detecting 8 bit changes

Hello!
I would like to make a VHDL circuit ( xilinx 9500 cpld, webpack 5.2 ) that would set the IRQ output if any of the eight inputs ( Din: in std_logic_vector(7 downto 0); ) changes it state. The IRQ should be cleared at the rising edge of the STR input. The problem is that I cannot detech vector input changes and I cannot change states of one output from two processes.

George

 

[Al Farouk]

Re: Detecting 8 bit changes

the problem is simple you can post your code so we can help.

 

[Vonn]

Re: Detecting 8 bit changes

I think the problem may be that you forget to put the inputs in your sensitivity list ; i said may be because i have faced this problem before and it was because of this reason

 

[Al Farouk]

Re: Detecting 8 bit changes

If the problem is due to the inclusion of the element in the sensitiviy list, Model sim will warn that the element should be included withtin the list.