VHDL association list error sld

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_syn_attributes.all;
 
entity shiftDrAdder is
    port
    (
-- {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!
        key : in  std_logic_vector(7 downto 0);
        led : out std_logic_vector(7 downto 0)
-- {ALTERA_IO_END} DO NOT REMOVE THIS LINE!
 
    );
 
-- {ALTERA_ATTRIBUTE_BEGIN} DO NOT REMOVE THIS LINE!
-- {ALTERA_ATTRIBUTE_END} DO NOT REMOVE THIS LINE!
end shiftDrAdder;
 
architecture ppl_type of shiftDrAdder is
  signal tdi : STD_LOGIC;
  signal tdo : STD_LOGIC;
  signal tck : STD_LOGIC;
--  signal tms : STD_LOGIC;
 
  signal cir : STD_LOGIC;
 
 
-- {ALTERA_COMPONENTS_BEGIN} DO NOT REMOVE THIS LINE!
  -- IR must have the modi
  -- 10, 01: read argument 1, 2
  --         according DR has length 2 bytes unsigned (could be 8 bits last 0)
  -- 11    : write result (suffices 8 bits to be read in at least into short) 
  -- 00    : write status (to be defined, spare) 
  component MyVJtag
    port(
      ir_out        : IN  STD_LOGIC_VECTOR (1 DOWNTO 0);
      ir_in     : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
      );
  end component;
 
-- {ALTERA_COMPONENTS_END} DO NOT REMOVE THIS LINE!
begin
-- {ALTERA_INSTANTIATION_BEGIN} DO NOT REMOVE THIS LINE!
 
 
  
  myVJtagInstance : MyVJtag port map (
    ir_out => key,
    virtual_state_cdr  => cir,--led(0),
    virtual_state_cir  => led(1),
    virtual_state_e1dr => led(2),
    virtual_state_e2dr => led(3),
    virtual_state_pdr  => led(4),
    virtual_state_sdr  => led(5),
    virtual_state_udr  => led(6),
    virtual_state_uir  => led(7),
    tdi => tdi,
    tdo => tdo,
    tck => tck
--    tms => tms,
    );
 
  led(0) <= cir;
  
-- {ALTERA_INSTANTIATION_END} DO NOT REMOVE THIS LINE!
 
end;

Code VHDL - [expand]
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virtual_state_cdr  => cir,--led(0),

Code VHDL - [expand]
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ENTITY MyVJtag IS
    PORT
    (
        ir_out      : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        tdo     : IN STD_LOGIC ;
        ir_in       : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
        tck     : OUT STD_LOGIC ;
        tdi     : OUT STD_LOGIC ;
        virtual_state_cdr       : OUT STD_LOGIC ;
        virtual_state_cir       : OUT STD_LOGIC ;
        virtual_state_e1dr      : OUT STD_LOGIC ;
        virtual_state_e2dr      : OUT STD_LOGIC ;
        virtual_state_pdr       : OUT STD_LOGIC ;
        virtual_state_sdr       : OUT STD_LOGIC ;
        virtual_state_udr       : OUT STD_LOGIC ;
        virtual_state_uir       : OUT STD_LOGIC 
    );
END MyVJtag;