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vhdl assertion question

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ricl

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I have this assertion statement:
...
begin
assert (data_out = expect);
report "data mismatch"
severity error;
...
my understanding is, only when data_out not equal to expect, the message "data mismatch" will display
I checked that data_out and expect are same, but I always see this message printed.
If I change expect to a wrong value, it reports "assertion violation" and print out "data mismatch" message. With the right value, only "data mismatch" message, no "assertion violation" message.

Anybody has an idea?
Thanks
 

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