VHDL "assert" vs "report"

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shaiko

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What is the difference between "assert" & "report" in VHDL ?
Please give an example of how the 2 are used.
 

I believe report is equivalent to assert false. However, there may be a bigger difference is the way that tools collect coverage data. Usually, you want to know the percentage of assert statements that evaluated true versus the total number of assert statements. And you may want to know the percentage of assert statements that never evaluated true or false. However, report statements are just informational messages with varying severities.
 
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shaiko said:
What is the difference between "assert" & "report" in VHDL ?
Please give an example of how the 2 are used.
Click to expand...
- Assert basically wraps a condition around when the report statement is executed.
- Assert can be used as a concurrent statement, report cannot.

assert not(my_sig /= other_sig and rising_edge(clock)) report "OOPS! my_sig equals other_sig" severity ERROR;

report "This is a basic report...make sure you put this inside a process";
report "This is a report with a severity level which can be used to stop the sim" severity ERROR;

Kevin Jennings
 
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