[SOLVED] VHDL and Verilog difference

Mina Magdy · Jul 25, 2013

could any one told me what is the different between (Variable in VHDL and reg in Verilog ) and (Signal in VHDL and wire in Verilog)

TrickyDicky · Jul 25, 2013

The things you mention are not comparable. You might as well ask whats the difference between an integer in C and the letter 'E'

Variables in VHDL similar to blocking assignments in verilog
Signals are like non-blocking in verilog

[SOLVED] VHDL and Verilog difference

Mina Magdy

Member level 3

TrickyDicky

Advanced Member level 7

Mina Magdy

OmegaRT

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[SOLVED] VHDL and Verilog difference

Mina Magdy

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TrickyDicky

Advanced Member level 7

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