vhdl and state machine

hello

are there a computer program that generate the code VHDL from state machine presentation?


i think that this migration can be done by a computer program but i don't know if such program exist

thank's

Yes. Something like simulink could do it, but you get much better results writing it yourself

TrickyDicky said:

Yes. Something like simulink could do it, but you get much better results writing it yourself

Click to expand...

even if i'm a begginer width VHDL an state machine :-o

can u tell me what kind of amelioration can i do width code generatate by simulink

amelioration?

Xilinx ISE used to have a state-machine to VHDL tool (StateCAD), but I believe it was dropped a while ago. It sucked. You would NEVER learn the proper way to write a state machine by looking at the crap that came out of statecad.

Writing state machines 'by hand' is not that hard and learning how to do it is important.

tahtouh said:

hello
are there a computer program that generate the code VHDL from state machine presentation?

i think that this migration can be done by a computer program but i don't know if such program exist
thank's

Click to expand...

A few questions for you to ponder first...my guesses at your answers are in parentheses
- To what standard would the 'state machine presentation' conform? (you probably don't know)
- What industry standards exist to define the 'state machine presentation'? (Ditto)
- What tools, standard or proprietary, exist that support editing a 'state machine presentation'? (Ditto)
- If such tools exist, can the 'state machine presentation' files be interchanged? (Ditto)
- If such tools exist, where can I locate one and take it out for a test run to see how usable it might be (Ditto)

Assuming my guesses at your answers are reasonably close to reality, then you should now ask yourself why would you want to use either proprietary or non-existent, possibly difficult to use tools to create a non-interchangable file that does not conform to any industry standards? Viewed in that light hopefully you would now consider your original posted question about converting 'state machine presentation' to VHDL to be moot.

Writing the state machine in VHDL avoids all these problems since the language is a defined standard with tools that approximately conform to that standard that are generally usable by those in the industry.

So, before you try to tackle the question that you posted, you should instead research to see if there are any graphical state machine tools that produce what you would consider a 'state machine presentation' that meets your usability and design portability goals and then ask if there is a tool to convert to VHDL. My guess is that if you find such a graphical tool, you will likely find that one of the outputs of that tool is VHDL or Verilog thus solving your problem and again rendering your original posted question moot.

Good luck on your search. I don't know of any such tools but that is mainly because I haven't looked or heard/read anyone discuss (favorably) such a tool. Even if one existed I likely wouldn't use it because the problem that such a tool would solve is of such low difficulty (to me), that it would likely be more work to insert another tool into the design tool chain. In short, I'm guessing that the benefit would not be worth the cost. Your cost/benefit ratio may be different and once I tried such a tool maybe I would find the cost/benefit to be more attractive, but right now just the search for that tool wouldn't clear the hurdle.

Kevin Jennings