Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

VHDL-AMS error: ADC_REF_LADDER' could not be loaded, entity may requre re-analysis

Status
Not open for further replies.

linan0827

Newbie level 3
Newbie level 3
Joined
Oct 22, 2007
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,310
Hi everyone!

I am following the Virtuoso AMS Designer Flow to practice the the simulation of the mixed-signal circuits. The simulation project is provided by Cadence, which is vfs_amsflow. When I compile the project all the components in Verilog-AMS is compiled correctly but the only one in VHDL-AMS has a error. The NCVHDL.log indicates the error is

ncvhdl_p: *E:ENNOFN (u/59/59/linan/vfs_amsflow/VFS_AMS_PHY180/adc_ref_ladder/adc_ref_ladder_behav/vhdl.vhms,19|50): Intermidiate file for entity 'ADC_REF_LADDER' could not be loaded, entity may requre re-analysis.
errors:1, warnings: 0
ncvhdl_p: *W,SPUNFW: specific library unit was never processed 'adc_ref_ladder:adc_ref_ladder_behav'.

I have no idea what should I do to fix this problem. Could anyone give me some solution? Thank you very much for your help in advance.

Li Nan
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top