carbon9
Member level 3
vhdl after statement
Hi,
I'm trying to use "after" statement to change some variables as the time passes as in the following code:
I simulate this design in Multisim. I use a 100 ns clock. When the machine is in stateA, according to the code, x must be logic 1 at t=10ns and the go to logic 0 at t=20ns. But in the simulations, x becomes logic 0 at t=20ns only. I can not see it in logic 1 between t=10ns and t=20ns. How can I solve this?
Regards
Hi,
I'm trying to use "after" statement to change some variables as the time passes as in the following code:
Code:
library ieee;
use ieee.std_logic_1164.all;
entity p82 is
port(a, c, clk, rst: in std_logic;
x: out std_logic);
end p82;
architecture behavior of p82 is
type state is (stateA, stateB);
signal pr_state, nx_state: state;
begin
-----Lower Section--------
process(rst, clk)
begin
if(rst='1') then
pr_state<=stateA;
elsif(clk'event and clk='1') then
pr_state<=nx_state;
end if;
end process;
---Upper Section----------
process(a, c, pr_state)
begin
case pr_state is
when stateA =>
x<='1' after 10 ns;
x<='0' after 20 ns ;
nx_state<=stateB;
when stateB =>
x<='0' after 10 ns;
x<='1' after 20 ns;
nx_state<=stateA;
end case;
end process;
end behavior;
I simulate this design in Multisim. I use a 100 ns clock. When the machine is in stateA, according to the code, x must be logic 1 at t=10ns and the go to logic 0 at t=20ns. But in the simulations, x becomes logic 0 at t=20ns only. I can not see it in logic 1 between t=10ns and t=20ns. How can I solve this?
Regards