[SOLVED] VHDL addition "1111"+"1111"=FAIL

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Hi.
I will explain my problem simply.
I'm trying to get summary of 4-bit vectors in one, 8-bit vector.

Code VHDL - [expand]
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signal cnt1,cnt2,cnt3,cnt4,cnt5 : STD_LOGIC_VECTOR (3 downto 0);
signal count                  : STD_LOGIC_VECTOR (7 downto 0);
 
cnt1 <= "0000";
cnt2 <= "0000";
cnt3 <= "0000";
cnt4 <= "0001";
cnt5 <= "1111";
 
count <= cnt1 + cnt2 + cnt3 + cnt4 + cnt5;


I'm expecting to get "00010000" on "count", but I get "00000000"

When I tried this:

Code VHDL - [expand]
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count <= "0000"&cnt1 + "0000"&cnt2 + "0000"&cnt3 + "0000"&cnt4 + "0000"&cnt5;


I got "00011111"

Yes, I have read recomendations, to use differnt library or use "integer", but I still fail to understand.
I add this:

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;


Is it not enough, or is it too much? How to get "00010000" in this example? How to use "integer" in this example?
In my project, each of the counters cnt1-cnt5 will have own reset signal, but I want to join them in to one vector, to make future processing. :-?
 

https://www.csee.umbc.edu/portal/help/VHDL/operator.html

"+" has higher precedence than "&". thus you get:
Code: 
count <= "0000" & (cnt1+"0000") & (cnt2+"0000") & (cnt3+"0000") & (cnt4+"0000") & cnt5;
-- "0000" & "0000" & "0000" & "0000" & "0001" & "1111"
-- one of the std_logic_* packages must allow the assignment to work despite the bit-width difference.

-- you want
count <= ("0000"&cnt1) + ("0000"&cnt2) + ("0000"&cnt3) + ("0000"&cnt4) + ("0000"&cnt5);
 
lucbra said:
why not using unsigned in stead of std_logic_vector for cnt and count?
Click to expand...

This would make sense from a standard VHDL point of veiw (assuming the OP got rid of std_logic_arith to ensure there were no clashes). But you would still have exactly the same problem.
 
Re: VHDL addition &quot;1111&quot;+&quot;1111&quot;=FAIL

yes true for the second piece of code - I was referring to the original part in post #1.
'+' has higher precedence than '&'
 
Presuming the poster want to learn reasonable VHDL coding style instead of using outdated libraries, I would suggest (with unsigned type for all signals)
Code: 
count <= resize(cnt1,8) + cnt2 + cnt3 + cnt4 + cnt5;

The other summands are automatically resized to 8-bit unsigned before being added. The advantage of resize() is that it also peforms sign extension for signed signals.
 
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