shaiko
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Hello,
Is it possible to define a 3D unconstrained array as an input port to a VHDL entity?
for example - inside a package
If I use the custom type "unconstrained_3D_array" as an input port to an entity - will it synthesize?
Is it possible to define a 3D unconstrained array as an input port to a VHDL entity?
for example - inside a package
Code:
type unconstrained_2D_array : is array ( natural range <> ) of std_logic_vector ;
type unconstrained_3D_array : is array ( natural range <> ) of unconstrained_2D_array ;