aeneas81
Junior Member level 1
scheduling output in vhdl
Hi all, I'm a beginner in VHDL language and would like to know is there any way I can schedule 2 output signal simultaneously? Coz in the first program I wrote, there's one clock delay between the input and the first output, and another clock delay between the first output and second output. Both the output depends only depends on a single input. By the way, is it possible to even eliminate the delay between the input and output?
Thanks a lot for you help!
Hi all, I'm a beginner in VHDL language and would like to know is there any way I can schedule 2 output signal simultaneously? Coz in the first program I wrote, there's one clock delay between the input and the first output, and another clock delay between the first output and second output. Both the output depends only depends on a single input. By the way, is it possible to even eliminate the delay between the input and output?
Thanks a lot for you help!
