vhdl 16-bit booth algorithm question

i'm a way down beginner at vhdl programming and just can't get what's wrong with this code! The error msg is "EOF syntax error" but dunno. How stressful.
I would really really REALLY appreciate it if someone can give me a hand with this.
please help =]

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity booth is
port (
reset : in std_logic;
clk : in std_logic;
load : in std_logic;
mlpcnd : in std_logic_vector (7 downto 0);
mlplr : in std_logic_vector (7 downto 0);
product : out std_logic_vector (15 downto 0)
);
end entity booth;

architecture rtl of booth is
signal q1 : st_logic;
signal ac : std_logic_vector (7 downto 0);
signal br : std_logic_vector (7 downto 0);
signal qr : std_logic_vector (7 downto 0);
signal sc : integer;
begin
process (reset, clk)
variable tmp_ac : std_logic_vector (7 downto 0);
begin
if (reset='0') then
br <= (others => '0');
qr <= (others => '0');
ac <= (others => '0');
q1 <= '0';
sc <= 8;
product <= (others => '0');
elsif(clk='1' and clk'event) then
if (load='1') then
br <= mlpcnd;
qr <= mlplr;
ac <= (others => '0');
q1 <= '0';
sc <= 8;
product <= (others => '0');
else
if (sc=0) then
product <= ac & qr;
else
if (qr(0)='0' and q1='1') then
tmp_ac := ac + br;
elsif (qr(0)='1' and q1='0') then
tmp_ac := ac + not br + '1';
else
tmp_ac := ac;
end if;
end if;
q1 <= qr(0);
qr <= tmp_ac(0) & qr(7 downto 1);
ac <= tmp_ac(7) & tmp_ac(7 downto 1);
sc <= sc - 1;
end if;
end if;
end process;
end architecture rtl;

Make these two changes:

(remove numeric_std)


and
(st_logic - check the spelling mistake)


--vipin
https://vhdlguru.blogspot.com/

thanks for the comment! i've tried but it still won't work.