library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_control is
port (
clock_50 : in std_logic;
sw : in std_logic_vector(9 downto 0);
vga_hs, vga_vs : out std_logic;
ledg : out std_logic_vector(9 downto 0);
vga_r, vga_g, vga_b : out std_logic_vector(3 downto 0)
);
end vga_control;
architecture behavior of vga_control is
signal vcounter : integer;
signal hcounter : integer;
signal clock : std_logic;
signal cl : unsigned(1 downto 0);
begin
ledg <= "1010101011"; -- ignore
-- 50 MHz to 25 MHz
clock <= cl(1);
process (clock_50, sw(9))
begin
if sw(9) = '1' then
cl <= "00";
elsif clock_50'event and clock_50 = '1' then
cl <= cl + "01";
end if;
end process;
vga_r <= "1111" when hcounter < 300 and vcounter < 300 else "0000";
vga_g <= "1111" when hcounter < 300 and vcounter < 300 else "0000";
vga_b <= "1111" when hcounter < 300 and vcounter < 300 else "0000";
process (clock, sw(9))
begin
if sw(9) = '1' then
hcounter <= 0;
vcounter <= 0;
vga_hs <= '1';
vga_vs <= '1';
elsif clock'event and clock = '1' then
if hcounter = 799 then
hcounter <= 0;
if vcounter = 524 then
vcounter <= 0;
else
vcounter <= vcounter + 1;
end if;
else
hcounter <= hcounter + 1;
end if;
-- the info I have is: visible area: 640, front porch: 16, back porch: 48, retrace: 96
if hcounter >= 656 and hcounter <= 751 then
vga_hs <= '0';
else
vga_hs <= '1';
end if;
-- the info I have is: visible area: 480, bottom: 10, top: 33, retrace: 2
if vcounter >= 490 and vcounter <= 491 then
vga_vs <= '0';
else
vga_vs <= '1';
end if;
end if;
end process;
end behavior;