very strange problem need help, pls

[lhlbluesky]

i have designed a SH(sample-holde) circuit, just as the picture shows (fig1). it consisits of four TG and two Buffer, IN is a changing signal, first, S1 is on, and IN is stored in C1 (just called IN1), then, S2 is on, IN (has changed) is stored in C2 (IN2). after a while, S3,S4 on at the same time, readout the difference of IN1 and IN2 (fig2). that is, S3 and S4 are the same signal.

originally, i use S3 and S4 for different ports in layout, and i add stimilus in the four ports, of course, S3 and S4 have the same stimilus, S3- and S4- have the same stimilus, and the simulation result is ok (12 bit resolution). while i want to connect S3 and s4, S3- and S4- together separately in layout, so only two ports needed. however, when rerun the simulation, the result is very bad, very different, only 8 bit resolution.

i'm sure that, i only connect them together in layout with a short wire (fig3), nothing else. but why? why does the resolution have such a big reduction? i cheched my layout, except the two connecting wire, no other change has made. but the simulation result is very strange, can any one help me? thanks all.

 

[lhlbluesky]

in fig3, only two stimilus added, one for S3(S4), one for S3-(S4-). i really need your help, thanks.

Added after 16 minutes:

and after i connect S3 and S4, S3- and S4-, the simulation result shows that, the resolution decline starts at the node after the first switch (that is, the positive end of buffer), but i have not changed that part, i only added the two short wire as fig3 shows. it is very strange, why?

 

[dick_freebird]

Why are S3/S4 not time-staggered the same as S1/S2?

Are you respecting the slew / settling time required for the
amplifiers to track the input? Look at the internal nodes,
the amplifier + and - inputs, and see if they are fully settled
before the next switch edge. Perhaps you have just added
too much loading for whatever the IN source impedance is,
or maybe OUT2 just needs more time than you have
given (if OUT1 is good but OUT2 is not).

These don't look like CAD schematics, so you might also look
for some typo in the netlist, that might be shorting nodes
and doubling capacitances, or such. Again probing the
intermediate nodes might show this (they should be time-
distinct, if not then you're getting close to finding a hookup
error I bet).

 

[lhlbluesky]

according to my system requirement, S3/S4 not time-staggered. besides, the amplifier + and - inputs are fully settled before the next switch edge, and the resolution decline starts at the node after the first switch (that is, the positive end of buffer), but i have not changed that part. very strange, why?

 

[lhlbluesky]

anyone can help me, or give me some advice?

 

[lhlbluesky]

what is the reason?

 

[erikl]

what is the reason?

Via your S3,S4 switches you are creating a short-circuit between 2 rather low-resistive buffer outputs. Assuming total symmetry, you'd get the center value between the 2 outputs. Total symmetry, however, is totally illusive, so you get any value in between.

 

[lhlbluesky]

hi, erikl, i don't understand what you said, can you speak it more clearly? thanks.

 

[erikl]

hi, erikl, i don't understand what you said, can you speak it more clearly? thanks.

So sorry, lhlbluesky, I was mistaken: My error was I thought your OUT1 & OUT2 were short-circuited, too. Sorry again!

I really don't know the reason for this strange behaviour. Try to find out if there possibly is a timing problem, as dick_freebird indicated. And check your S1, S2 switch signals if there is (more) cross-talk from S3, S4 when both pairs are shorted.

Are both +inputs of the buffers affected equally by the resolution degradation, or differently? If differently, different cross-talk could be the reason. Would stronger driving of S1, S2 change anything?

No more ideas, currently, sorry!