xsound
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Hi guys, I need some help in simply (for people who know vhdl quite well) project of processor. Below I put project assumptions, some of them are already done, but highly possible that are wrong wrote in vhdl. Please, any kind of help I will never do it myself.
Processor project:
Data bus and address bus are 16 bits.
1) List of commands:
MOV arg1, arg2 - shift arg2 in arg1 (arg1 - register, arg2 - address or register)
ADD arg, arg2 - addition arg2 to arg1, result in arg1 (arg1 - register, arg2 - address or register)
SUB arg, arg2 - substraction arg2 from arg1 result in arg1 (arg1 - register, arg2 - address or register)
BINtoBCD arg1 (conversion value binary into BCD, result in arg1)
RDCTRL arg1 (load register marker to arg1 - register or address in memory)
WRCTRL arg1 (record register marker from arg1 - register or address in memory)
ASHL arg1, arg2 (arithmetic shift into left of value in arg1 of arg2-bits; arg1 -register, arg2 - register or constant 3-bit, result in arg1)
ASHR arg1, arg2 (arithmetic shift into right of value in arg1 of arg2-bits; arg1 -register, arg2 - register or constant 3-bit, result in arg1)
IF it is needed, set markers C,Z,S,P.
2)Records (registers)
* ES - register of segment (16 bit register stores the address of the block)
* AP1, AP2 - registers address 8 bit for stores address of shift)
3)System of cooperation with memory - way of segmentation
Range segments: 9 bits
Range shifts: 7 bits
I attached files with clear code were received from leader from my univesity - everything was done in Quartus12.
I noticed here many people well know vhdl, and I guess for you it's few minutes. IF someone could look at code, would be great.
Many thanks in advance.
And below I also attached what is done (but probably wrong - many errors while trying to compilate code)
ALU:
Processor project:
Data bus and address bus are 16 bits.
1) List of commands:
MOV arg1, arg2 - shift arg2 in arg1 (arg1 - register, arg2 - address or register)
ADD arg, arg2 - addition arg2 to arg1, result in arg1 (arg1 - register, arg2 - address or register)
SUB arg, arg2 - substraction arg2 from arg1 result in arg1 (arg1 - register, arg2 - address or register)
BINtoBCD arg1 (conversion value binary into BCD, result in arg1)
RDCTRL arg1 (load register marker to arg1 - register or address in memory)
WRCTRL arg1 (record register marker from arg1 - register or address in memory)
ASHL arg1, arg2 (arithmetic shift into left of value in arg1 of arg2-bits; arg1 -register, arg2 - register or constant 3-bit, result in arg1)
ASHR arg1, arg2 (arithmetic shift into right of value in arg1 of arg2-bits; arg1 -register, arg2 - register or constant 3-bit, result in arg1)
IF it is needed, set markers C,Z,S,P.
2)Records (registers)
* ES - register of segment (16 bit register stores the address of the block)
* AP1, AP2 - registers address 8 bit for stores address of shift)
3)System of cooperation with memory - way of segmentation
Range segments: 9 bits
Range shifts: 7 bits
I attached files with clear code were received from leader from my univesity - everything was done in Quartus12.
I noticed here many people well know vhdl, and I guess for you it's few minutes. IF someone could look at code, would be great.
Many thanks in advance.
And below I also attached what is done (but probably wrong - many errors while trying to compilate code)
ALU:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ALU is
port ( A : in signed(15 downto 0);
B : in signed(15 downto 0);
Salu : in bit_vector (3 downto 0);
LDF : in bit;
clk : in bit;
Y : out signed (15 downto 0);
C,Z,S : inout std_logic
);
end entity;
function to_bcd ( bin : std_logic_vector(7 downto 0) ) return std_logic_vector is
variable i : integer:=0;
variable bcd : std_logic_vector(11 downto 0) := (others => '0');
variable bint : std_logic_vector(7 downto 0) := bin;
begin
for i in 0 to 7 loop -- repeating 8 times.
bcd(11 downto 1) := bcd(10 downto 0); --shifting the bits.
bcd(0) := bint(7);
bint(7 downto 1) := bint(6 downto 0);
bint(0) :='0';
if(i < 7 and bcd(3 downto 0) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(3 downto 0) := bcd(3 downto 0) + "0011";
end if;
if(i < 7 and bcd(7 downto 4) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(7 downto 4) := bcd(7 downto 4) + "0011";
end if;
if(i < 7 and bcd(11 downto 8) > "0100") then --add 3 if BCD digit is greater than 4.
bcd(11 downto 8) := bcd(11 downto 8) + "0011";
end if;
end loop;
return bcd;
end to_bcd;
architecture rtl of ALU is
begin
process (Salu, A, B, clk)
variable res, AA, BB,CC: signed (16 downto 0);
variable CF,ZF,SF : std_logic;
begin
AA(16) := A(15);
AA(15 downto 0) := A;
BB(16) := B(15);
BB(15 downto 0) := B;
CC(0) := CF;
CC(16 downto 1) := "0000000000000000";
case Salu is
when "0000" => res := AA; -- mov
when "0010" => res := AA + BB; --add
when "0011" => res := AA - BB; --sub
when "0001" => res := to_bcd(AA); -- BINtoBCD
when "1111" => res(16) := AA(16);
res(15 downto 0) := AA(16 downto 1); --shift (wrong!)
end case;
Y <= res(15 downto 0);
Z <= ZF;
S <= SF;
C <= CF;
if (clk'event and clk='1') then
if (LDF='1') then
if (res = "00000000000000000") then ZF:='1';
else ZF:='0';
end if;
if (res(15)='1') then SF:='1';
else SF:='0'; end if;
CF := res(16) xor res(15);
end if;
end if;
end process;
end rtl;