Verilog's integer and reg?

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davyzhu

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Hi all,

I heard that Verilog has integer type.
Someone said integer can be signed or unsigned.
How to declare signed integer?

And what's the difference with integer and reg signed [31:0](2's complement) ?

Any suggestions will be appreciated!
Best regards,
Davy
 

I guess you cannt specifically declare signed or unsigned integer as in C language. THe value will be stored as signed when you declare integer. there is no difference between reg [31:0] and integer for synthesis.
 

integer is signed 32 bit.

the difference between signed reg 32 bit and integer...

I was told that for integer, if the value reach the maximum, e.g. 32'h7FFF_FFFF, no matter what value u add in, the value will remain as 32'h7FFF_FFFF.

but for signed reg, if u add 1 for 32'h7FFF_FFFF, the value will go to 32'h0000_0000.

I have no time to verify that. Tell me if you have verified that
 

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    davyzhu

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integer will roll to 0 when overflow,same as reg, it can be used in compare expression,like (i<-1).
 


Please see the Verilog-2001 spec.

Thomson
 

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