VerilogA Warning VACMP-1047 "more than one module"

[edwina]

Dear edaboard members,

I am new to VerilogA and I have a question related to the Spectre VACOMP-1047 warning. I am trying to fabricate a Voltage Controlled Delay Line (VCDL) in VerilogA which is build up out of Voltage Controlled Delay Cells (VCDC). I include the VCDC into the VCDL to make multiple instances of it. However Spectre gives the following warning:

WARNING (VCOMP-1047): The Verilog-A file contains more than one module definition. ADE canprocess only one module per Verilog-A file. Put only one module in each Verilog-A file so that ADE can idenfity pin names, directions, and hierarchy within each separate module.

I don't understand what I am doing wrong. Making instantiations of module A in module B, is a thing that is even done in the Cadence Verilog-A Language Reference guide. The only way to access module A in file B is, as far as I know, via includes. Do you have any suggestions or tips?

I think I am using version 6.1.7-64.b.500.4 of the cadence IC design suite.

The code of the VCDL

// VerilogA for DLL_ideal, VCDL, veriloga

`include "constants.vams"
`include "disciplines.vams"


`timescale 1s/1ps

module VCDL (in, delay_control, out);
input in, delay_control;
output [0:7] out;

electrical in, delay_control;
electrical [0:7] int_node;
electrical [0:7] out;

	VCDC VCDC0(in, int_node[0], delay_control);
	VCDC VCDC1(int_node[0], int_node[1], delay_control);
	VCDC VCDC2(int_node[1], int_node[2], delay_control);
	VCDC VCDC3(int_node[2], int_node[3], delay_control);
	VCDC VCDC4(int_node[3], int_node[4], delay_control);
	VCDC VCDC5(int_node[4], int_node[5], delay_control);
	VCDC VCDC6(int_node[5], int_node[6], delay_control);
	VCDC VCDC7(int_node[6], int_node[7], delay_control);

analog begin
	V(out[0]) <+ V(int_node[0]);
	V(out[1]) <+ V(int_node[1]);
	V(out[2]) <+ V(int_node[2]);
	V(out[3]) <+ V(int_node[3]);
	V(out[4]) <+ V(int_node[4]);
	V(out[5]) <+ V(int_node[5]);
	V(out[6]) <+ V(int_node[6]);
	V(out[7]) <+ V(int_node[7]);
end
	

endmodule

`include "<the right directory>/VCDC/veriloga/veriloga.va"

Note that the include of the VCDC is on the bottom. Otherwise Spectre wil use the netlist of the VCDC instead of the VCDL so the pinout of the VCDL will be wrong (maybe it does it due to the warning of this tread, namely it only processes the first module of the file). Keeping the include at the bottom works around this problem.

The code of the VCDC

// VerilogA for DLL_ideal, VCDC, veriloga


`include "constants.vams"
`include "disciplines.vams"

module VCDC (in, out, delay_control);
	output out;
	input in, delay_control;
	electrical out, in, delay_control;
	parameter real  max_delay = 1;


analog begin

V(out) <+ absdelay(V(in), V(delay_control), max_delay);

end
endmodule

Thank you very much in advance!

 

[ThisIsNotSam]

don't include the second file, instead pass both files to the tool separately. the use of `include is a poor strategy except for few very specific cases like the inclusion of 'global' constants.

 

[edwina]

Dear Sem (or maybe not Sem),

Thank you very much for your reply. Your statement seems to be in accordance with what the spectre HDL compile complains about. However I have no clue how to pass the VCDC-module to the VCDL-module without using the "`include"-statements. Could you provide in a helping hand in this lacking knowledge?