Hi all,
I am trying to check in VerilogA, if a file exists.
Reason: if it exists, I dont want to overwrite it, but create a new one.
I was trying to teach VerilogA
- to try to open the file in read mode.
- if that fails, then the file would not exist and I would open it in write mode.
- otherwise the file would exist and I create a new one.
The problem, which I am facing, is that opening a file for read-only will generate a fatal error in the cadence simulator, which stops the simulation.
Is there a way to circumvent this?
Any help is welcome.
BR
Maurits