[Verilog] What is zero delay loop?

Hello All,

Can anyone help me to understand - what is zero delay loop in verilog?

Thanks in advance.

-Maulin Sheth

assign a = !b;
assign b = !c;
assign c = !a;

values cannot be determined. If there were a delay between elements, it would be a simple ring oscillator and would have defined behavior.

permute said:

assign a = !b;
assign b = !c;
assign c = !a;

values cannot be determined. If there were a delay between elements, it would be a simple ring oscillator and would have defined behavior.

Click to expand...

Hello parmute,

Thank you very much for quick response.
Sorry but can you give me the detailed explanation - what you want to say through example.

Thanks in advance
-Maulin Sheth

This is also called a "combinatorial loop". The basic issue is that the current value for a signal depends on itself (the current value of the signal.

A practical example might be two designers who have a misunderstanding:
designer 1 believes his module should send a "stop" signal immediately when his module cannot accept new data AND new data is being marked as valid. (stop = full and valid)
designer 2 believes his module should immediately mark output as not valid when the stop signal is asserted. (valid = available and not stop).

In this case, if available=0 or full=0, things will logically have no problems. If either is tied to a constant 0, there won't even be a combinatorial loop. However:
stop = full and (available and not stop). If full = 1 and available = 1 then stop = not stop. stop is a binary value, but neither stop=1, nor stop=0, make the logic correct. No value for stop can be determined.

The problem can be solved if the designers either agree that: stop = full, or that valid = available. Both have been used in practical systems.