zongya
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Hi all,
I just start to learn verilog and try to simulate AND gate on eda playground.
The module is:
And testbench is:
However, the waveform I got is only from 0~15 time units. Shouldn't it be 20 units since I put four #5?
I'm using a online simulation website https://www.edaplayground.com/ Tool & Simulators ModelSim 10.1d
I just start to learn verilog and try to simulate AND gate on eda playground.
The module is:
Code:
module andgate (a, b, y);
input a, b;
output y;
assign y = a & b;
endmoduleAnd testbench is:
Code:
module andgate_tb;
wire t_y;
reg t_a, t_b;
andgate my_gate( .a(t_a), .b(t_b), .y(t_y) );
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0, my_gate);
$monitor("At time %2t, t_a=%d t_b=%d t_y=%d",$time, t_a, t_b, t_y);
t_a = 1'b0;
t_b = 1'b0;
#5;
t_a = 1'b0;
t_b = 1'b1;
#5;
t_a = 1'b1;
t_b = 1'b0;
#5;
t_a = 1'b1;
t_b = 1'b1;
#5;
end
endmoduleHowever, the waveform I got is only from 0~15 time units. Shouldn't it be 20 units since I put four #5?
I'm using a online simulation website https://www.edaplayground.com/ Tool & Simulators ModelSim 10.1d