"Verilog vs VHDL" ain't a soccer game

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Regnum

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verilog game

Here is the most objective reference I've found, concerning the "Verilog vs VHDL" issue. It includes an interesting feature-by-feature comparison table.

Sorry for breaking the "don't-post-VHDL-vs-Verilog-stuff" rule. The paper is worthwhile.
 

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