Verilog: Using force comman in the DUT..

nohj_yar · Jan 28, 2015

HI all!

I understand that the force command is not supported by synthesis. Is there any way to write it in the DUT? Or is there a way to force a signal (without using the force command) inside the DUT without writing it in the testbench instead write it inside the DUT?

THanks...

MSBR · Jan 28, 2015

Well, I don't really understand your point, I m sorry for that. A force command completely overrides the signal value. If you want some signal to have particular value all the time, you can use "localparam" and if you want to assign some particular values to a signal you can use assign fro wires and always block for registers.

Please provide some examples to elaborate your question.

Thanks.
MSBR

dave_59 · Jan 28, 2015

The force statement is a debugging aid, and hack for unfinished descriptions. Typically a force is used with a hierarchical reference to a signals to circumvent the normal operation of the DUT.
So you need to describe the normal operation of the signal in question, and what you want the force to accomplish.

Verilog: Using force comman in the DUT..

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Verilog: Using force comman in the DUT..

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