verilog transport delay in non-blocking and blocking assignment

dave_59 said:

Two are differences: the non-blocking assignment does block the process the statement is in; the blocking assignment - blocks. The blocking assignment schedules an update of the LHS as soon as the statement completes, and the non-blocking assignment always schedules the update of the LHS at some time after the statement completes.

If you had the follwoing code, and assuming reg1 was 1 and reg2 was 2:

Code:

begin 
  $display("Display1 %t reg1: %d, reg2: %d", $time, reg1, reg2);
  reg1 = #10 reg2 ;
  reg2 = #10 reg1 ; 
  $display("Display2 %1 reg1: %d, reg2: %d", $time, reg1, reg2);
end

The first display statement would show the values 1 and 2, and 20 time units later the second $display statement would show the values 2 and 2. That is because the update to reg1 happens at time+10 before the second assignment statement executes.

If you had

Code:

begin 
  $display("Display1 %t reg1: %d, reg2: %d", $time, reg1, reg2);
  reg1 <= #10 reg2 ;
  reg2 <= #10 reg1 ; 
  $display("Display2 %1 reg1: %d, reg2: %d", $time, reg1, reg2);
  #10 $display("Display3 %1 reg1: %d, reg2: %d", $time, reg1, reg2);
  #1 $display("Display4 %1 reg1: %d, reg2: %d", $time, reg1, reg2);
end

The first two display statements would always display the same values for reg1 and reg2 at the same time regardless of the delay (the old values), and thew would both display in order at the same time. The third display statement will also the old values, but 10 time units later. The updates to the LHS occur after all the other things scheduled for that time slot have executed. The 4th display statement will display the updated values, 2 and 1.

There is no good reason to use the blocking assignment with a delay.

Click to expand...