verilog to vhdl conversion?????

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while converting from verilog to VHDL which will be converted as signals which will be converted as variables????or
is it totally depend on the design????:?:
 

in vhdl signals are the intermediate connections between the gates and modules. these signals are defined as wires in verilog
 

thanks
what about registers, how to interpret that which will be converted as signals or variables????
 

Yes, its all about the behavioural description. Signals behave like non-block assignments in Verilog and Variables like blocking.
A signal can become a register, but so can a variable. It all depends on usage.
 
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