aswathymohan
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- Nov 11, 2012
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I am using Xilinx ISE Project navigator (P.28d) for writing the verilog code for vending machine. Whats wrong with my code? So many warnings, but no errors.Pl help..it too urgent
Code:
module vend(
input clk,
input reset,
input cancel,
input sel1,
input sel2,
inout [6:0] money,
input Rs_10,
input Rs_20,
output reg product,
output reg [6:0] change,
output reg [6:0] returns
);
wire wait_1,wait_2;
reg st_1,st_2,st_3,st_4;
wire pr_1,pr_2;
reg nx_1,nx_2;
reg snacks,coffee;
reg snack_c,coffee_c;
reg [6:0] money_count;
always @(posedge clk)
begin : count
if (sel1==1)
begin
if(pr_1==1)
begin
nx_1<=wait_1;
if((Rs_10) & ~(Rs_20))
begin
nx_1<=st_1;
money_count=(money_count+7'b0001010);
if(money_count>=7'b0011110)
begin
nx_1<=snacks;
change<=({0,money_count}-7'b0011110);
snack_c<=snack_c-1;
disable count;
end
nx_1<=wait_1;
if(cancel==1)
begin
returns<=({0,money_count});
disable count;
end
end
if(~(Rs_10) &(Rs_20))
begin
nx_1<=st_2;
money_count=(money_count+7'b0010100);
if(money_count>=7'b0011110)
begin
nx_1<=snacks;
change<=({0,money_count}-7'b0011110);
snack_c<=snack_c-1;
disable count;
end
nx_1<=wait_1;
if(cancel==1)
begin
returns<=({0,money_count});
disable count;
end
end
end
end
else
begin
snack_c<=1'd4;
nx_1<=reset;
product<=0;
end
if (sel2==1)
begin
if(pr_2==1)
begin
nx_2<=wait_2;
if((Rs_10) & ~(Rs_20))
begin
nx_2<=st_3;
money_count=(money_count+7'b0001010);
if(money_count>=7'b0101000)
begin
nx_2<=coffee;
change<=({0,money_count}-7'b0101000);
coffee_c<=coffee_c-1;
disable count;
end
nx_2<=wait_2;
if(cancel==1)
begin
returns<={0,money_count};
disable count;
end
end
if(~(Rs_10) &(Rs_20))
begin
nx_2<=st_4;
money_count=money_count+7'b0010100;
if(money_count>=7'b0101000)
begin
nx_2<=coffee;
change<=({0,money_count}-7'b0101000);
coffee_c<=coffee_c-1;
disable count;
end
nx_2<=wait_2;
if(cancel==1)
begin
returns<=({0,money_count});
disable count;
end
end
end
end
else
begin
coffee_c<=1'd4;
nx_2<=reset;
product<=0;
end
end
endmodule
nx_1<=snacks;
change<=({0,money_count}-7'b0011110);
snack_c<=snack_c-1;
disable count;
end
nx_1<=wait_1;
if(cancel==1)
begin
returns<=({0,money_count});
disable count;
end
end
if(~(Rs_10) &(Rs_20))
begin
nx_1<=st_2;
money_count=(money_count+7'b0010100);
if(money_count>=7'b0011110)
begin
nx_1<=snacks;
change<=({0,money_count}-7'b0011110);
snack_c<=snack_c-1;
disable count;
end
nx_1<=wait_1;
if(cancel==1)
begin
returns<=({0,money_count});
disable count;
end
end
end
end
else
begin
snack_c<=1'd4;
nx_1<=reset;
product<=0;
end
if (sel2==1)
begin
if(pr_2==1)
begin
nx_2<=wait_2;
if((Rs_10) & ~(Rs_20))
begin
nx_2<=st_3;
money_count=(money_count+7'b0001010);
if(money_count>=7'b0101000)
begin
nx_2<=coffee;
change<=({0,money_count}-7'b0101000);
coffee_c<=coffee_c-1;
disable count;
end
nx_2<=wait_2;
if(cancel==1)
begin
returns<={0,money_count};
disable count;
end
end
if(~(Rs_10) &(Rs_20))
begin
nx_2<=st_4;
money_count=money_count+7'b0010100;
if(money_count>=7'b0101000)
begin
nx_2<=coffee;
change<=({0,money_count}-7'b0101000);
coffee_c<=coffee_c-1;
disable count;
end
nx_2<=wait_2;
if(cancel==1)
begin
returns<=({0,money_count});
disable count;
end
end
end
end
else
begin
coffee_c<=1'd4;
nx_2<=reset;
product<=0;
end
end
endmodule
Some of the warnings which i got
Xst:1710 - FF/Latch <returns_0> (without init value) has a constant value of 0 in block <vend>. This FF/Latch will be trimmed during the optimization process.
Xst:1710 - FF/Latch <change_0> (without init value) has a constant value of 0 in block <vend>. This FF/Latch will be trimmed during the optimization process.
Xst:2677 - Node <money_count_0> of sequential type is unconnected in block <vend>.