Verilog Testbench to monitor signal relationship

Status
Not open for further replies.

aspirinnnnn

Member level 1
Joined
Jan 4, 2012
Messages
33
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
Beijing,China
jetyoung.72pines.com
Activity points
1,511
I am currently working on a CMOS Image Sensor controller. this controller has to give a huge control signals to the ADC and Pixel array. those signals has its fixed relationship like:
a is pull up high for 10 clock,then pull down for 15 clock and .....
b is pull up high one clock behind the a ,and then stay high for xxx clock
c is ........

how do i achieve auto automatically test in testbench, thanks for any helps
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…