Verilog testbench help!! (bit urgent)

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dpaul said:
Send all *relevant* source code either as an attachment or copy+pasted here with code_tags (in the text-box editor menu, see the # option).
Click to expand...
They can't post any of their "top" secret code, nor can they reveal anything by posting a testcase example of code, so that we can determine what needs to be changed to fix their problems.

:thinker:I think the OP is a troll and we've been suckered into feeding it.
 

Sorry this is confusion and I am not a troll please

I would try to explain again and you guys from fresh try to help me genuinely:-

Problem: I have to read a continuous hex file such as 0000 ffff 0000 ffff acac 0000 .... ....... etc etc
and assign the value read to tb_b = data[15:8]
tb_a = data[7:0]

I don't have a solution and I am asking you guys to help me get one:
Code: 
           initial
             begin
           while(cond) begin
               $readmemh("video_data.txt",f_data,0, 2**32);
                tb_b = data[15:8];
                tb_a = data[7:0];
   ........

   end;

I want to do something like this?? Can you please help ??
 

All contributors to the thread have been calling for thread closure if the OP continuous to withhold relevant code details.

Thread closed now.
 
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