Verilog testbench help!! (bit urgent)

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Thanks very much TrickyDricky.

The problem is in the original testbench the same things worked while assigning values to inout signals directly and it didn't complain but the verilog one complains when you assign the directly. (so the need to probe the enables)?? I really don't know how to deal with this error (illegal inout ports vsim -3053)??? What is my solution then??
 

Then clearly your Verilog does NOT do what the VHDL did.
The solution would be to make the Verilog work the same.
That is as much as we can say without the VHDL and the new Verilog.
 


the solution is for you to study verilog.
 

TrickyDicky said:
Then clearly your Verilog does NOT do what the VHDL did.
The solution would be to make the Verilog work the same.
That is as much as we can say without the VHDL and the new Verilog.
Click to expand...

Thanks very much TrickyDicky for all your help and everyone who tried to help

On another note; I have another problem, in my simuation some of my reset signals to from 0 to H state and they are causing Xes in my solution. Can anyone plaese advise me what can I do that it dosen't go to H state. Many thanks
 

On another note; I have another problem, in my simuation some of my reset signals to from 0 to H state and they are causing Xes in my solution
Click to expand...

Again we don't have the VHDL nor the Verilog code.
A reset signal is supposed to be either 0 or 1. So find out from where the reset signal is being driven (probably from the TB). Follow all the code lines where the reset is assigned a value.
Either you should do it or put here the original and complete code for others to do it.

btw - In this forum members always create a new topic for new problems, suggestions.

This is a small guide as to what should be done when you see X propagation in a sim: https://www.techdesignforums.com/practice/guides/x-propagation/
 
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Without the code. No clue.
H state is supposed to mean "Weak Logic High" and is really meant for analogue modelling. It doesnt exist in standard 4-state verilog.
 

TrickyDicky said:
Without the code. No clue.
Click to expand...

No kidding!

They aren't even making an attempt to improve their description of the issues or supply a decent example of the problem using a testcase or useful code that can be examined in context. All sonika111 keeps supplying are out of context snippets that don't tell us anything besides, they have no clue what they are doing.

I suspect the VHDL testbench they are trying to convert to Verilog is garbage. I'd wager the VHDL DUT they are trying to simulate is probably also garbage.
 

Thanks very much for all your help with the little information that I could give. Really appreciate your help and apologise that I could not share much


I am unable to display strings from my txt file which are in "....................".

Also I am unable to see the variables from the testbench which are not on the ports. Any help there would be really appreciated.

Many thanks
 

Have you not shared it because you dont want to show off how terrible the code is?
Use the object viewer to find the variables you need
 

TrickyDicky said:
Have you not shared it because you dont want to show off how terrible the code is?
Use the object viewer to find the variables you need
Click to expand...

I can't see them on object viewer either. Also
I am unable to display strings from my txt file which are in the form "Blah Blah Blah ".

Mnay thanks

- - - Updated - - -

Right .... I have a big txt file containg 32bit hex value repeated in a single continuos line like 0000 0f0h 0acc ...... ...... etc

Are these two lines not appropriate to do the job

p= $fgets(line,fd);
n_items=$sscanf(line,"%h",f_data);
Click to expand...

Beacuse at the moment it does not read this while

while in the VHDL testbench

ReadLine(f,in_line);
HREAD(in_line, f_data);
Click to expand...

does read this type of file. Please have a look to help. Many thanks

- - - Updated - - -

It seems it is keeps on reading the first 32 bit hex value again and again... does not read the next one....
 

It doesn't work because the Verilog statements aren't equivalent to the VHDL ones.
Learn Verilog.
 

Going back to your first post..
I think, if you'd have stuck with the VHDL, you could have shipped by now.
This wanting an SV testbench is costing you time, and time is money.
If you worked at my company, you'd probably be fired by now.
 


Have a look at the code in the link below and use it in your testbench, do the necessary changes in your testbench. Why dont you use Google?

https://stackoverflow.com/questions/16630319/how-to-read-a-text-file-line-by-line-in-verilog
 

Thanks for all your replies. The things you can help without helping the code can you please help those like
1.the problem above
2. display strings from my txt file which are in "....................".
3. I am unable to see the variables from the testbench which are not on the ports.

I would really appreciate that. Many thanks
 


send the txt file.
 

I am nearlly at the end and thanks for all your help. If you guys can plaese help in these three things.
1. The problem above which is critical
2.display strings from my txt file which are in "Blab blah Blah".
3. I am unable to see the variables from the testbench which are not on the ports.

I would appreciate your help
Mnay thanks

- - - Updated - - -

Thanks for your reply This is what I did and doesn't work
p= $fgets(line,fd);
n_items=$sscanf(line,"%h",f_data);
Click to expand...

- - - Updated - - -

Do I need to use $fread and $readmemh; but it dosen't seem to work

reg [31:0] data[0:2**32];
n_items=$fread(data,fd,0,2**32);
or
//$readmemh("test.txt",data);
Click to expand...

Can't get it right?? Can you please advise
 

How do I send the txt file??

If that is needed I would send?/ but I have already tried telling it has 32 bit hex values in a row 0000 0ffff acac 0000 0000 bbaa ...... ...... ( so many of them)

Thanks
 

Send all *relevant* source code either as an attachment or copy+pasted here with code_tags (in the text-box editor menu, see the # option).

else

post #56
 
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