Verilog/Sysverilog Test Bench Question

[Digital-L0gik]

how to access register from testbench

I am writing a test bench for a DUT I designed. However, I would like to use some flag signals that are within the DUT hierarchy at the test bench level to kick off some testing procedures. These flag signals are not part of my primary i/o to the DUT. How can I utilize these lower level DUT signals in my higher level test bench?

 

[anant]

testbench for register file in verilog

If you want to use the rtl signal that does not come out on the pin. you should access it hierarchically in the testbench.

 

[Digital-L0gik]

Yeah I heard about doing that, but I am not sure what the syntax is do that. Is this how you do it? Will this also work for signals that are even lower than the dut?

module y(...);
.....
reg flag1;


endmodule: y
 

module x(...);
.....
reg flag2;

y  i1  (....)  //instantiate y

endmodule: x

//--------------------------------------------
module xtb();
x  i ( ....);   //instantiate dut.

always @(i.flag2 or i.i1.flag1)
case(i.flag)
....


endmodule: xtb

 

[ljxpjpjljx]

just like the common usage in SV , you can get the signal in the design !

 

[pra]

For example if you have testbench file as top.v where u instantiated dut and in that dut u want to access a register x in the block blka

then u need to use top.dut.blka.x (u can use force n release to change irrespective what its driven to x)

hope this helps in clear understanding

 

[Digital-L0gik]

Thanks for the help, it is clear now!

 

[fpga_asic_designer]

hi pra, i agree with your point. but i think that kind of expression can only apply for verilog.

wut should be used for vhdl? i know in ncsim you can use some special function, but it can only be recognized with ncverilog.

For example if you have testbench file as top.v where u instantiated dut and in that dut u want to access a register x in the block blka

then u need to use top.dut.blka.x (u can use force n release to change irrespective what its driven to x)

hope this helps in clear understanding

 

[pra]

I am not confident on VHDL but I feel same will be there in that otherwise it becomes very tough to verify large designs in VHDL.
Lot of EDA companies will use VHDL for their designs too...
May be somebody who r expert in VHDL can tell you about this

hi pra, i agree with your point. but i think that kind of expression can only apply for verilog.

wut should be used for vhdl? i know in ncsim you can use some special function, but it can only be recognized with ncverilog.

For example if you have testbench file as top.v where u instantiated dut and in that dut u want to access a register x in the block blka

then u need to use top.dut.blka.x (u can use force n release to change irrespective what its driven to x)

hope this helps in clear understanding