Verilog/SystemVerilog ForLoop 7Segment Display

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Mavnus04

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Hi all,

I am trying to display different numbers on 8 7-segment displays. With the code below, I am able to display the numbers 7 to 0.
However, I do not want to use i as the reference for my case statement. I want to use 'add', but all the displays show the same number when I declare it as an integer, wire or reg.

Code: 
module segtest(
	output [6:0] hex [0:7]);
	
	//reg [3:0] add = 4'h0;
	//integer add;
	//wire add;
	reg [6:0] num1 = 7'h79; 
	reg [6:0] num2 = 7'h24;
	reg [6:0] num3 = 7'h30;
	reg [6:0] num4 = 7'h19;
	reg [6:0] num5 = 7'h12;
	reg [6:0] num6 = 7'h02;
	reg [6:0] num7 = 7'h78;
	reg [6:0] num8 = 7'h00;
	reg [6:0] num9 = 7'h18;
	reg [6:0] num0 = 7'h40;	
	reg [6:0] numA = 7'h08;
	reg [6:0] numB = 7'h03;
	reg [6:0] numC = 7'h46;
	reg [6:0] numD = 7'h21;
	reg [6:0] numE = 7'h06;
	reg [6:0] numF = 7'h0E;
	reg [6:0] curr;
	
	always @(*) begin
		for(integer i=0; i<8; i=i+1'b1) begin
			//add <= add + 1'b1;
			case(i)
				4'h0: curr = num0;
				4'h1: curr = num1;
				4'h2: curr = num2;
				4'h3: curr = num3;
				4'h4: curr = num4;
				4'h5: curr = num5;
				4'h6: curr = num6;
				4'h7: curr = num7;
				4'h8: curr = num8;
				4'h9: curr = num9;
				4'hA: curr = numA;
				4'hB: curr = numB;
				4'hC: curr = numC;
				4'hD: curr = numD;
				4'hE: curr = numE;
				4'hF: curr = numF;
				//default: curr = 4'h0;
			endcase
			hex[i] = curr;
		end
	end
			
endmodule //segtest

Any and all help would be great! Thank you.
 

Because you can't perform increments (counters) in a combinational always block. add <= add + 1'b1 implies a storage element in a combinational block as you have a feedback of add in the RHS. So instead the for loops through to the end and only the last value for i (or add) will be applied to the case statement.

As you are writing Verilog as a software program...you neglected to deal with the concept of parallelism and time. Verilog for loops are unrolled into logic for each i value. And in the case of a combinational always block there is no concept of time without statements like wait which aren't synthesizable. What you need to do is add a clock and use a counter to divide down the clock to something like 250-500 ms so you can see the values.

Of course you'll probably use the output of one of the counter bits or the terminal count as a clock, don't do that. It's a very poor design practice that increases the complexity of the timing constraints and reduces maximum clock frequency of a design. Instead compare your counter to the terminal count value and register that compare to create a single clock wide enable pulse. Use that to enable your counter (add) and generate the hex outputs.

Regards
 

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