[SOLVED] Verilog Synthesis using Synopsys Design Compiler

Hi,

I am trying to perform gate-level simulation of my circuit using Synopsys Design Compiler.

My program runs during functional simulation and I get the right result as compared with my C code. I then used Synopsys and performed the Analyze -> Elaborate -> Compile Design steps and saved the netlist generated as well as the .sdf delay file. On running the same testbench on the synthesized code, I found out that I wasn't getting the right results. I looked at the waveform file generated to see what was going on and found out that nothing in the main.v program is running (see attached screenshot). I mean, none of the always blocks in the main.v program are running. It looks like I messed up while performing synthesis, but I have done it a lot of times following the instructions, so can someone tell me what I am missing?

Thanks,

Faisal.

You see just because the verilog code is functional doesnt mean that it will be synthesise to correct netlist. there will be some construct in verilog file which is supported by verilog but not properly understood by the DC tool.
a) You can try to synthesize each of the sub blocks and see if they are coming out properly.
b) The usual culprits are case statements or accumulator
Please use divide and conquer to handle this problem.... also there might issue with function statement in the .lib that you are using.

artmalik said:

You see just because the verilog code is functional doesnt mean that it will be synthesise to correct netlist. there will be some construct in verilog file which is supported by verilog but not properly understood by the DC tool.
a) You can try to synthesize each of the sub blocks and see if they are coming out properly.
b) The usual culprits are case statements or accumulator
Please use divide and conquer to handle this problem.... also there might issue with function statement in the .lib that you are using.

Click to expand...

Thank you. I stripped the top module off everything including the included modules, and started with one always block at a time. Took me a long time, but finally figured it out and pinpointed it to a few places, one at a time. Thanks for the idea of 'divide and conquer.' I am never going to forget that!!!

Thanks,

Faisal.