[SOLVED] Verilog synthesis problem!Please Help

module Log_max(v,n_var,T);

input [31:0]v;
output [31:0]n_var;
output reg [31:0] T=0;
wire [31:0] v;
reg [31:0]n_var;
reg [3:0] base = 2;


//floor of the log base 2
function integer CLogB2;
input [31:0] Depth;
reg i;
begin
i = Depth;
for(CLogB2 = 0; i > 1; CLogB2 = CLogB2 + 1)
i = i >> 1;
end
endfunction

always @ (v)
begin
n_var = CLogB2(v);
T = 2 ** n_var;
end
endmodule

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module Log_max_tb;

// Inputs
reg [31:0] v;

// Outputs
wire [31:0] n_var;
wire [31:0] T;


// Instantiate the Unit Under Test (UUT)
Log_max uut (
.v(v),
.n_var(n_var),
.T(T)
);

initial begin
v = 2614;

end



endmodule

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I think you're missing the 'begin' and 'end' keywords that should enclose the code inside the for loop.

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module Log_max(v,n_var,T,clk);

input clk;
input [31:0]v;
output [31:0]n_var;
output reg [31:0] T;
wire [31:0] v;
reg [31:0]n_var;
//reg [3:0] base = 2;

//floor of the log base 2

function integer CLogB2;
input [31:0] Depth; //pseudo input port which remains unused throughout the program
integer i;
begin
//i = Depth;
i= 2614;
for(CLogB2 = 0; i > 1; CLogB2 = CLogB2 + 1)
i = i >> 1;
end
endfunction

always @ (posedge clk)
begin
n_var = CLogB2(v);
//T = base ** n_var; This is unsynthesizable. Can only be simulated

T = 2 ** n_var;


end
endmodule

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module Log_max_tb;

// Inputs
reg [31:0] v;
reg clk;

// Outputs
wire [31:0] n_var;
wire [31:0] T;

// Instantiate the Unit Under Test (UUT)
Log_max uut (
.v(v),
.n_var(n_var),
.T(T),
.clk(clk)
);

initial begin
// Initialize Inputs
v = 0;
clk = 0;

// Wait 100 ns for global reset to finish
#100;

v = 2614;
clk = 1;


end
endmodule

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