verilog syntax error

tok47 · Jul 11, 2013

Hi ALL,

I having a verilog compilation error. Need help adn guidance.

I have a instance connected as below,

USB_A0 U1 (
.PLLDIVM(1'b0),
.PLLDIVK[1](1'b0),
);

I have a compilation error :
Error-[SE] Syntax error
token is '['

Can I know how to solve this?

Thanks.

Rdgs
YY

FvM · Jul 11, 2013

Verilog LRM says:

12.3.6 Connecting module instance ports by name

The second way to connect module ports consists of explicitly linking the two names for each side of the connection: the port declaration name from the module declaration to the expression, i.e., the name used in the module declaration, followed by the name used in the instantiating module. This compound name is then placed in the list of module connections. The port name shall be the name specified in the module declaration. The port name cannot be a bit-select, a part-select, or a concatenation of ports. If the module port declaration was implicit, the port_expression shall be a simple identifier or escaped identifier, which shall be used as the port name. If the module port declaration was explicit, the explicit name is used as the name of port.

In other words, you can only use a simple port name (e.g. PLLDIVK) on the left side of the named port connection. If the port is a vector, you have to specify an expression for all bits in the paranthesis.

mail4idle2 · Aug 15, 2013

USB_A0 U1 (
.PLLDIVM(1'b0),
.PLLDIVK({1'b0,1'b0}), //For a 2 bit vector connection
);

verilog syntax error

tok47

Advanced Member level 4

FvM

Super Moderator

mail4idle2

Full Member level 4

Similar threads

verilog syntax error

tok47

Advanced Member level 4

FvM

Super Moderator

mail4idle2

Full Member level 4

Similar threads

Privacy & Transparency

Privacy & Transparency