Verilog "Switch-level" of circuit description has it equivalent in VHDL?

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FlyingDutch

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Hello,

I am learning myself Verilog (in which I haven't big expierience). During studying tutorial concerning Verilog features I encountered some topics concerning "Switch-level" of circuit description. This is level of description in one can use transistors switches and capacitors. I was a bit surprised because in my previous expierience with VHDL I never
heard of this level of abstraction in design description.

I have in connection with this two questions:

1) Does software for synthesis Xilinx ISE and Vivado and Intel Quartus supports this level of abstraction in circuit description during synthessis and implementation?

2) Has VHDL language counterpart for "Switch-level" level of abstraction?

Thanks and Regards
 

Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

FPGA logic implementation uses configurable logic elements as low level primitives not transistors. In so far "switch level" is useless for FPGA implementation. Switch level description could be translated to FPGA logic nevertheless.

Switch level can be at least emulated in VHDL using std_ulogic states.
 
Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?


Hello,

I mean for example simulation of capacitive network, like on this screenshot:


The course I am reading is concerning FPGA designing using Verilog, but maybe this topic is related to designing ASIC (but it is not specified that it is not related to Veerilog with FPGA)?

Thanks and Regards
 

Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

The screenshot is an excerpt from Verilog reference IEEE 1800-2012, clause 6.6. I doubt that ASIC tools are supporting synthesis of capacitive networks, but the topic is beyond my experience. Do you know a simulation tool that could handle the example?

I'm not aware of a similar concept in VHDL.
 
Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?


Hello,

I was surprised than I red about this level of abstraction in context of designing FPGAs in Verilog. This coures is a shortcut from a lectures of "Programable devices" subject in one of Polish Technical Universites. I just asked this question by curiosity. I for sure has much less expierience in this subject than you. I don't know any software tool or simulator that supports this feature.

Thanks for your answer and regards
 

Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

All major simulation tools support Verilog switch-level primitives. People who design FPGAs (not the users who program them) may utilize switch level primitives, especially in the simulation of the I/O pads. People who build the gate-level libraries of of ASICs will also use this, as well as people doing custom IC design.

VHDL does not have this capability.
 
Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?


just to clarify dave's answer: we make use of this verilog feature for modelling purposes, not to design. this low level of description is not RTL and therefore not synthesizable. you can simulate it just fine, but that is the end of it.
 
Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

ThisIsNotSam said:
just to clarify dave's answer: we make use of this verilog feature for modelling purposes, not to design. this low level of description is not RTL and therefore not synthesizable. you can simulate it just fine, but that is the end of it.
Click to expand...
Just to correct ThisIsNotSam's answer, one can take a nettist of gate/switch-level primitives and feed it to an IC layout tool.
 

Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

dave_59 said:
Just to correct ThisIsNotSam's answer, one can take a nettist of gate/switch-level primitives and feed it to an IC layout tool.
Click to expand...

I have never seen a single analog designer in my lifetime that does schematic design in verilog. there might be some, but it certainly is not a industry-wide practice.

and my point was that it is not synthesizable, which is still correct.
 

Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

Hello guys,

I am a bit confused again. Could you answer my additional questions:

1) Software tools for designing ASICs also use Verilog?

2) These tools can use "switch-level" descriptions for synyhersis and simulation?
.
3) What are examples of such tools (their names and producers)?

This is still only my curiosity , I will never use this "switch level" in my designs.

Regards
 

Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

The flow for asic is similar to fpga. You write rtl, synthesise, place, route, timing analysis. Asic has the additional steps of actually designing the chip, pin out, masks, emulation (often using fpgas).

The tools are also by vendors you've probably heard of. I think the biggest is cadence as it has tools to do all of the flow, but there's also synopsis and mentor that provide tools for various parts of the flow.

Any code you can use on fpga can also be used on asic, but code style will depend on the vendor primitives library you're using. But most of it is portable.
 
Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

1) Yes, verilog is the preferred language for ASIC design. However, verilog has many flavors within itself. You need to write SYNTHESIZABLE verilog.
2) Only for simulation.
3) Cadence genus and Innovus. Synopsis DC and ICC.
 
Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

There are still some applications where traditional logic synthesis tools do not produce optimal results, so other means must be used. Sometime people do draw schematics by hand, or have scripts that generate netlist structures from template generators. Those netlists can be used for simulation, layout and verification between netlist and layout, See https://en.wikipedia.org/wiki/Layout_Versus_Schematic
 
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