Verilog, specify block

[incisive]

verilog specify

Where would u specify timing checks for a verilog simulator?
and interconnect delay?

 

[eeeraghu]

verilog specify block

I beleive specify timing checks in the specify block itself,replacement is done using the back annotation i.e sdf file,
even i am not sure but hopeit is right

 

[AlexWan]

specify in verilog

Hi incisive,

Your meaning specify the hierachical timing check in the Verilog simulator or select different ways to do timing check in simulator?

Please clear it.

 

[eeeraghu]

specify block verilog

A specify block defines the timing section of the module in a separate block. As a result, the
functional verification becomes independent of the timing verification. The specify block can
remain unchanged at different levels of abstraction.
A specify block is bounded by the keywords specify and endspecify, and must appear within
a module definition.
Do not confuse specify parameters (keyword specparam, short for specify parameter) with
module parameters (keyword parameter). You declare module parameters outside a specify
block, and use them to configure instances of the module. You declare specparams inside a
specify block, and use them as timing constants.
This subsection describes specify block parameters, module path delays, pulse filtering
controls, and timing checks.