3wais
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I have written a verilog file that implements some arithmetic operations, I defined my signals as
or
. when I simulate that on isim simulator it does the operation as specified, with signed arithmetic. but when I simulate the same file in modelsim it behaves as if the signals are unsigned!
I have to use modelsim because I need to load some memory files (Isim does not load memory files, you have to load the memory by hand!) so I need to get this fixed. how to make modelsim interpret the signals as signed? in operation not in wave viewer of course?
Code:
wire signed
Code:
reg signedI have to use modelsim because I need to load some memory files (Isim does not load memory files, you have to load the memory by hand!) so I need to get this fixed. how to make modelsim interpret the signals as signed? in operation not in wave viewer of course?