wls
Member level 4
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rtl gate sdf
Hello guys. How do u make adjustment to testbench ( rtl ) to verify that the verilog netlist ( from dc or fpga ) that backannotate with sdf is correct with the rtl simulation ?
Once u synthesis with dc/fpga like xilinx . You with have gate delay ( sdf ) . How to make proper adjustment to the pure rtl testbench for the delay .
Does any one have simple example with explanation/doc to adjust/change and verify that both rtl and gate simulation is correct .
If have rtl with testbench and synthesis of the rtl netlist with modify testbench example would be great . Plus little explanation.
Thx.
Hello guys. How do u make adjustment to testbench ( rtl ) to verify that the verilog netlist ( from dc or fpga ) that backannotate with sdf is correct with the rtl simulation ?
Once u synthesis with dc/fpga like xilinx . You with have gate delay ( sdf ) . How to make proper adjustment to the pure rtl testbench for the delay .
Does any one have simple example with explanation/doc to adjust/change and verify that both rtl and gate simulation is correct .
If have rtl with testbench and synthesis of the rtl netlist with modify testbench example would be great . Plus little explanation.
Thx.