Verilog: push button starts sequence

`timescale 1ns / 1ps

module countonpb(
    input clock, pb,
    output reg [3:0] msbs,
    output reg [3:0] lsbs,
    output reg [6:0] sevseg,
    output reg [3:0] an,
	 output reg [1:0] clk
    );
	reg [3:0] i;
	reg [3:0] j;
	integer count_a = 0;
	integer count_50M = 0;
	reg pb_press;

	initial begin
		an[0] <= 0;
		an[1] <= 1;
		an[2] <= 1;
		an[3] <= 1;
		i <= 9;
		j <= 9;
	end		
	
	always @ (posedge clk[0])
	begin
		an[0] <= ~an[0];
		an[1] <= ~an[1];
		an[2] <= 1;
		an[3] <= 1;
		msbs <= i;
		lsbs <= j;
	end
	
	always @ (posedge clk[1])
	begin
		pb_press <= pb;
		if (pb_press == 1)
		begin
			if (i == 0)
			begin
				i = 0;
				j = j - 1;
			end
			else
			begin
				if (j == 0)
				begin
					i = i - 1;
					j = 9;
				end
				else 
					j = j - 1;
			end
		end
	end


	always @ (posedge clk[0])
	begin
	if (an[1])
	begin
		case(msbs)
			0: sevseg = 7'b0000001;
			1: sevseg = 7'b1001111;
			2: sevseg = 7'b0010010;
			3: sevseg = 7'b0000110;
			4: sevseg = 7'b1001100;
			5: sevseg = 7'b0100100;
			6: sevseg = 7'b0100000;
			7: sevseg = 7'b0001101;
			8: sevseg = 7'b0000000;
			9: sevseg = 7'b0000100;
			default: sevseg = 7'b0000001;
		endcase
	end
	if (an[0])
	begin
		case(lsbs)
			0: sevseg = 7'b0000001;
			1: sevseg = 7'b1001111;
			2: sevseg = 7'b0010010;
			3: sevseg = 7'b0000110;
			4: sevseg = 7'b1001100;
			5: sevseg = 7'b0100100;
			6: sevseg = 7'b0100000;
			7: sevseg = 7'b0001101;
			8: sevseg = 7'b0000000;
			9: sevseg = 7'b0000100;
			default: sevseg = 7'b0000001;
		endcase
	end
	end

	always @ (posedge clock) //slower clock
		if (count_50M < 25000000) count_50M = count_50M + 1;
		else
		begin
				clk[1] = ~clk[1];
				count_50M = 0;
		end
		
	always @ (posedge clock) //slow clock
		if (count_a < 25000) count_a = count_a + 1;
		else
		begin
			clk[0] = ~clk[0];
			count_a = 0;
		end

endmodule