adscrz
Member level 1
Verilog problem
...
assign MCU_P2 = OE ? 8'hZZ : temp ;
...
Original design intention is when the OE is low, output temp to MCU_P2 , when the OE is high , output the ZZ to MCU_P2 .
Imitate with the ModelSim the result is right, but when I run it in my test board:
If the OE is high, the MCU_P2 value is a FF,
If the OE is low, the MCU_P2 worth temp value,
But the problem is when OE become high again , and always for high, however the MCU_P2 = temp ???!!!
And why is not the FF of the expectation,
why?
Thanks
...
assign MCU_P2 = OE ? 8'hZZ : temp ;
...
Original design intention is when the OE is low, output temp to MCU_P2 , when the OE is high , output the ZZ to MCU_P2 .
Imitate with the ModelSim the result is right, but when I run it in my test board:
If the OE is high, the MCU_P2 value is a FF,
If the OE is low, the MCU_P2 worth temp value,
But the problem is when OE become high again , and always for high, however the MCU_P2 = temp ???!!!
And why is not the FF of the expectation,
why?
Thanks