Verilog problem regarding tristate pins

[adscrz]

Verilog problem

...
assign MCU_P2 = OE ? 8'hZZ : temp ;
...
Original design intention is when the OE is low, output temp to MCU_P2 , when the OE is high , output the ZZ to MCU_P2 .
Imitate with the ModelSim the result is right, but when I run it in my test board:
If the OE is high, the MCU_P2 value is a FF,
If the OE is low, the MCU_P2 worth temp value,

But the problem is when OE become high again , and always for high, however the MCU_P2 = temp ???!!!
And why is not the FF of the expectation,

why?
Thanks

 

[mc_navman]

Re: Verilog problem

You have not connected tristate pins all the way through. At some point your pins are output only. Make sure that this module and the pin definition is input output.

I mean tristate.

 

[visualart]

Verilog problem

If u don't use the bus, the tri shall hold the last state ,i.e. hte FF is the HiZff

 

[nagraj]

Re: Verilog problem

Well I found the similar problem in VHDL program.Is it necessary in VHDL too drive the bus to tristate logic.Even though I tried with using tristate logic it didn't work...(Big surprise).

well someone can address this problem...It will be great.