[SOLVED] verilog port connection

[xpratx]

hi,

i am new to verilog and i have a question. i don't know if it is possible or not.

i have a project 3 modules now i want to connect a output port of one module to input port of another module if input of third module satisfy some condition.

anyone could explain with a small example?

 

[chipmonkey]

you can connect a mux to the input of the required module. you can use the condition as select signal and connect the outputs of previous modules as input for the mux.

 

[ljxpjpjljx]

just like c <= condition ? a : b;