Verilog "parameter" error...

[davorin]

Does this sound familiar to someone?

""C:/verilog/test/tools.v", line 32: Error, syntax error near: parameter <- Error(s) found in Verilog source."

With the error line:

"parameter TEST = 8'b00000001;"

 

[jelydonut]

The only thing I can think of is that you may have the parameter located outside of the module.. I always just put them after the port declaration..

jelydonut