Verilog Memory Design

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I already have drawn out the block diagrams and SRAM and SIMMs but I always have a very difficult time with verilog. Can anyone help me or show me a good example that I could base it off of? I looked but couldn't find many useful information. This is designing a 64x8 memory unit with using 16x4 SIMMs. It seems simple enough but verilog always gives me a hard time.

Particularly I need to understand how to do the 64x8 memory unit module.
 
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16x4 memories?

that would mean 4x2 memory array of 16x4 devices. So you'll need to generate enables x4 (write, read, etc i.e. one of each enable type per pair of 16x4 devices (=16x8)) and will need to have a 4-bit address and 8-bit data.

As you didn't give enough of a detailed spec I can't say whether the data should be divided into read and write ports, bi-directional, synchronous/asynchronous interface.

Don't see why using Verilog is such an issue. Just draw the schematic of the design you need to run the SRAM and then translate it to Verilog using standard templates for coding synthesizable registers.

Regards
 


It seems simple but I have a difficult time as we were just thrown into verilog, I keep trying to understand it but it just doesn't get to me. I don't know if I need to spend more time on it. I mean I draw the whole memory fine and I know verilog is just simply taking that drawing and putting it into verilog. An example would help but I couldn't find any that's why.
 

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