verilog - library cell info needed

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powercore

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I need to run accurately a gate-level simulation, using Verilog, and I can't find rising and falling time delay of basic gates (not to mention the complex gates I need) under different load conditions (i.e. 1,2,3,4 NOT gate).
Technology is not an issue. How can I extract those info from a standard cell library if I could find one?
Can anybody help? if so PM me!
 

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